The evolution in Moore's Law means a shift away from processor performance to system performance. To achieve improved system performance, novel materials such as back end of line low-k dielectric materials, thinner gate oxide films and/or high-k gate dielectric films must be implemented. These materials represent challenges to conventional failure analysis involving new failure modes. In addition, strain induced device enhancements for PMOS and NMOS devices already implemented at 90 nanometer node with improved electron mobilities and hole mobilties can introduce new failure modes. To achieve requisite system performance for sub 45 nanometer nodes, novel structures such as two dimensional FINFET designs will be required challenging conventional failure analysis localization and analysis.