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| Session 12: Failure Analysis Process 1 | ||||
| Location: Meeting Room J1-J2 (San Jose McEnery Convention Center) | ||||
| (Please check final room assignments on-site). | ||||
| Session Description: The papers in this session show the breadth and depth of failure analysis process applied to a variety new challenges. Included are examples of innovative approaches added surmount unique problems. Papers in this session are valuable not only for the specific approaches introduced, but also as examples of adjusting the FA process to solve new problems. | ||||
| Session Chair: | Mr. David L. Burgess Accelerated Analysis, Half Moon Bay, CA | |||
| 9:50 AM | Failure Analysis Methodology of Li-Ion Incidents | |||
| 10:15 AM | Case Study and Fault Modelling for Wrong Redundancy Evaluation on DRAM Devices | |||
| 10:40 AM | Fault Isolation of Soft P-N Junction Break Down Due to Plasma Charging | |||