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| Session 14: System Level Analysis and Test | ||||
| Location: Meeting Room J3 (San Jose McEnery Convention Center) | ||||
| (Please check final room assignments on-site). | ||||
| Session Description: | ||||
| Session Chair: | Mr. Michael Lane Intel Corporation, Hillsboro, OR | |||
| 11:00 AM | PCB Related Field Failures with ImAg Surface Finishes | |||
| 11:25 AM | Laser Based Failure Isolation Techniques | |||
| 11:50 AM | Series Capacitance in High Speed Differential Pairs, a Failure Analysis Case Study | |||
| 12:15 PM | Concepts for In Situ Diagnostics in Analog Microelectronic Circuits | |||
| 12:40 PM | Wireless Advanced Failure Analysis Tool | |||