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| Yield, Test and Diagnostics | ||||
| Location: Meeting Room E145 (Oregon Convention Center ) | ||||
| (Please check final room assignments on-site). | ||||
| Session Description: | ||||
| Session Chairs: | Mr. Tracy Myers ON Semiconductor, Gresham, OR Mr. Kendall Scott Wills Independent Consultant, Sugar Land, TX | |||
| 8:15 AM | Logic Diagnostics: Techniques, Applications and Challenges | |||
| 10:15 AM | Break | |||
| 10:30 AM | From Scan Testing to Embedded Testing | |||
| 12:00 PM | Luncheon | |||
| 1:00 PM | Defect-Oriented Testing | |||
| 3:15 PM | Break | |||
| 3:30 PM | Yield Basics for Failure Analysis including 300mm wafer and Cu technology | |||
| 4:30 PM | FA Case Histories using ATPG and SCAN Diagnostics: | |||