C. Changqing, H. Younan, Chartered Semiconductor Mfg Ltd, Singapore, Singapore

Summary: As device feature size continues to shrink, the reducing gate oxide thickness put more stringent requirement on gate dielectric quality in terms of defect density and contamination concentration. As the result, it becomes more difficult in analyzing gate oxide integrity and dielectric breakdown failures in wafer fabrication. Using traditional FA flow and methods, the root cause may be unclear, although some defects were observed after electrical fault isolation using emission microscopic tools such as EMMI and TIVA. In this paper, we will propose an new failure analysis flow of the GOI failure to improve FA’s success rate. In this new proposed flow, both chemical method (Wright Etch) and SIMS analysis techniques are employed to identify root cause of the GOI failures. In general, the shape of the defect might provide information of the GOI failure, whether related to PID or contamination. However, these Wright etch results are inadequate to answer the questions of whether the failure is caused by contamination or not, what is the contaminant and where it comes from. From the Wright etch results; GOI failure can be attributed to contamination or PID. If the failure is confirmed to be due to contamination, SIMS is used to further determine contamination source at ppm-ppb level. A real case of GOI failure will be discussed and presented. Using the new failure analysis flow, the root cause was identified to be iron contamination introduced from a worn out part made from stainless steel.