C. Schmidt, M. Simon, F. Altmann, Fraunhofer Institute for Mechanics of Materials, Halle, Germany; A. Nowodzinski, CEA-LETI Minatec, Grenoble Cedex 9, France

Summary: On-going miniaturisation combined with increasing integration density and functionality leads to extreme challenges for failure localization in complex multi chip devices. Mostly, direct optical access to inner structures is not available because of the three dimensional built up. Therefore standard techniques for failure localization like emission microscopy, OBIRCH or liquid crystal thermography are limited or not useful. Furthermore, target preparation, e.g. Cross sectioning of small sized defect structures can be also challenging because mechanically polishing is not precise enough and focused ion beam techniques are unsuitable for a whole chip stack. This paper presents the combination of defect localisation by Lock-in-Thermography (LIT) and cross-section preparation at defect structures of multi-chip-modules and demonstrates a complete failure analysis flow at high ohmic chip to chip interconnects.