35th International Symposium for Testing and Failure Analysis (November 15-19, 2009): A Transistor Level Failure Analysis Via Nano- Probing and Junction Stain TEM to Reveal 65nm Device Lightly Doped Drain Profile Abnormality

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A Transistor Level Failure Analysis Via Nano- Probing and Junction Stain TEM to Reveal 65nm Device Lightly Doped Drain Profile Abnormality

Tuesday, November 17, 2009: 2:45 PM
Meeting Room J3 (San Jose McEnery Convention Center)
Ms. Jie Su , Semiconductor Manufacturing International (Beijing) Corp, Beijing, China
Sanan Liang , Semiconductor Manufacturing International (Beijing) Corp, Beijing, China
Yoyo Wen , Semiconductor Manufacturing International (Beijing) Corp, Beijing, China
May Yang , Semiconductor Manufacturing International (Beijing) Corp, Beijing, China
Linfeng Wu , Semiconductor Manufacturing International (Beijing) Corp, Beijing, China
Chorng Niou , Semiconductor Manufacturing International (Beijing) Corp, Beijing, China
Xianfeng Chen , Semiconductor Manufacturing International (Shanghai) Corp, Shanghai, China
Gary Zhao , Semiconductor Manufacturing International (Beijing) Corp, Beijing, China
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