Failure Analysis of Present and Future DRAM Devices

Successful failure analysis of DRAM components is not possible without preparative measurement techniques and electrical analysis. This presentation depicts, which testing methods fulfil the necessary conditions for a successful physical failure analysis. A short introduction to the defect problems of highly integrated DRAM components will be followed by a functional description of the DRAM. It will shown by means of failures within the cell array, how localization can be achieved by the Bitmapping technique. The limit of the Bitmapping technique is the defect localization in the periphery of the DRAM. This limit can be resolved by the Soft-Defect-Localization (SDL) technique.