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Wednesday, November 17, 2010 - 4:50 PM
13.5

A Novel Technique for Localization of Low Level Leakage in Integrated Circuits

A. Chiang, H. Wu, H. Nguyen, W. Pratchayakun, P. Le, Vishay Siliconix, Santa Clara, CA

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Summary: Existing fault isolation techniques that detect the induced response to electrical and/or probing beam have their limit in localizing low level leakage. We present a novel technique to first highlight the location of low level leakage using the reaction of material to localized heat generated by the leakage under an appropriate electrical bias at some carefully chosen elavated temperature. The technique allows us to detect weakness in a trench power MOSFET caused by design or process that was deemed undetectable previously.