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Tuesday, November 16, 2010 - 2:10 PM
3.3

Inter Layer Dielectric Defect Induce High Contact Resistance

W. S. Hu, TSMC (Taiwan Semiconductor Manufacturing Company, Ltd.), Hsinchu, Taiwan; J. Higgins, R. L. Chiu, T. Kinder, J. Tyni, J. Chung, S. Ying, WaferTech LLC, Camas, WA

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Summary: High contact resistance is one key parameter of semiconductor devices that could significantly affect the products performance, causing yield loss and even potential reliability concerns. The causes of this problem is very complex including insufficient contact etching, particle blocking, abnormal Ti/TiN glue layer, tungsten plug deposition and post tungsten chemical mechanical polish clean issues. Insufficient failure analysis work may cause misleading information based on interpretation of the images resulting in longer time for solving the root problem.We have shown that by combining different analysis tools such as SEM, FIB, TEM/EDX and SIMS analysis the root cause of high contact resistance contacts can easily be determined. This was further confirmed by duplicating the failure mechanism using an experimental wafer and recreating the atmosphere that created the resistivity change.