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| Session 2: FA Process/Case Studies | ||||
| Location: Malachite Showroom (InterContinental Hotel Dallas) | ||||
| (Please check final room assignments on-site). | ||||
| Session Description: | ||||
| Session Chairs: | Rose Ring SMSC Austin, Austin, TX Dr. Leo G. Henry ESD-TLP Consulting & Testing, Fremont,, CA | |||
| 1:20 PM | 3.1 | Volume Electrical Failure Analysis for Product-Specific Yield Ramp | ||
| 1:45 PM | 3.2 | Case Study in Fault Isolation of a Metal Short for Yield Enhancement | ||
| 2:10 PM | 3.3 | Inter Layer Dielectric Defect Induce High Contact Resistance | ||
| 2:35 PM | 3.4 | Failure Analysis Methodology On Systematic Defect in ADC_PLL Ring Pattern Due to Plasma De-Chuck Process | ||
| 3:00 PM | 3.5 | Fault Isolation of Sub-Surface Lakage Defects Using Electron Beam Induced Current Characterization in Next-Generation Flash Memory Technology Development | ||
| 3:25 PM | 3.6 | A Case Study: Observation of Counter Doping of Gate Poly and Its Validation in High Density 90nm CMOS SRAM Bitcell | ||