C. Howard, K. Erington, S. Subramanian, Y. Tsang, R. Mulder, J. Bartlett, Freescale Semiconductor, Inc., Austin, TX

Summary: Precise isolation of failures has become more challenging on devices processed at the 130nm node and beyond. The inability to access many signals in lower metal layers increases uncertainties when isolating a fault by topside analysis. In the case of backside analysis, uncertainty is primarily because of the interpretation of Time Resolved Light Emission (TRLEM) waveforms. Therefore, more reliance on nanoprobe measurement techniques is required. Typically, the nanoprobe measurements are pseudo-static transistor characterization routines searching for leaky or resistive paths. A resistive connection to a gate node is undetectable using typical nanoprobing measurements. While nanoprobe capacitance-voltage techniques [1-2] can be used to characterize such resistive connections, they also require additional instrumentation and careful interpretation. This paper discusses a method of resolving the problem of detecting anomalous resistances or electrical barriers in the path to a poly-silicon gate node.