P. Tabary, Altis Semiconductor, Corbeil-Essonnes, France; B. Delahaye, H. Fray, J. P. Brun, N. Guilbaud, S. Lariviere, D. Basso, Altissemiconductor, Corbeil-Essonnes, France, France; M. Modi, M. Idir, Synchrotron Soleil, Gif-Sur-Yvette Cedex, France

Summary: Electrical resistance of M1/M3 stack for Aluminium based technology showed anomalous values when no Ti is inserted between AlCu and cap TiN. Process investigations lead to suspect formation of AlN layer at this interface. Blanket wafers were processed at different temperatures to reproduce the layer formation and characterized by numerous techniques including XPS and EELS-TEM profiling. Full use of the different results shows the formation of a very thin (a few nms) and highly resistive AlN layer at the cap TiN / AlCu interface as well as a thicker but less resistive AlN layer at the bottom TiN / AlCu interface. PVD process changes were attempted to reduce the M1/M3 stack resistance. Modification of the N2/Ar flow ratio for TiN sputtering shows slightly more stoechiometric TiN with reduced stack resistance by 35%