S. Kasapi, J. Liao, B. Cory, NVIDIA, Santa Clara, CA; I. Kapilevich, R. Portune, Y. S. Ng, C. Kardach, DCG Systems, Fremont, CA; E. Cheng, Spirox, Hsinchu, Taiwan

Summary: Yield on specific designs often falls far short of the yield predicted from foundry test vehicles, especially in new technology nodes. Improving yield on specific product wafers is an expensive and time-consuming problem. We present a workflow to integrate a limited set of electrical failure analysis (EFA) techniques to improve the speed and efficiency of product-specific yield ramp.