ISTFA Home   •   Exposition   •   To Register   •   ASM Homepage
Back to "Session 20: Packaging and Assembly Level FA II" Search
  Back to "Symposium" Search  Back to Main Search

Thursday, November 18, 2010 - 4:25 PM
20.3

Resolving the Failure Analysis Challenges On Stack Die Structure in Lead Frame Chip Scale Package (LFCSP)

J. C. P. Salimbangon, R. G. Mendaros, Analog Devices Inc, Brgy. Javalera, Gen. Trias, Cavite, Philippines

View in WORD format

Summary: Access to critical die and package structures for failure analysis purposes is complicated in stacked die devices in small packages such as thin 3 x 5 x 1.45mm, 14 lead, plastic LFCSP. The essential concern is exposing the bottom die and wire bonding profiles while maintaining electrical functionality in preparation for extensive visual examination and fault isolation. This technical paper discusses the failure analysis solutions developed to effectively access the areas of interest. Figure 1 and 2 shows the die stack construction and a packaged part respectively.