A. G. Boon, Globalfoundries, Singapore, Singapore

Summary: In this paper, a low yield case relating to a systematic ring pattern signature due to ADC_PLL failure on the low yielding wafers will be studied. The systematic problem solving process based on the application of a variety of FA techniques such as TIVA, AFP current Imaging, layout path tracing, PVC and XTEM together with Fab investigation is used to understand the root cause as well as failure mechanism proposed. This process is particularly critical on wafer foundry in which there is minimal available data on the test condition setup to duplicate the exact failure. The ring pattern was due to systematic open Via as a result of polymer built-up from plasma de-chuck issue. It would serve as a good reference to wafer Fab that encountered such issue