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| Session 3: Packaging and Assembly Level FA I | ||||
| Location: Lalique Ballroom (InterContinental Hotel Dallas) | ||||
| (Please check final room assignments on-site). | ||||
| Session Description: The packaging and assembly session deals with failures and fault isolation techniques associated with the chip as a whole unit. Technical talks in this session cover the wire bond process, wire bond pads, organic and ceramic chip packages, and chip package interactions. In addition interesting case studies demonstrating novel fault isolation applications to the chip and package as a unit are invited. | ||||
| Session Chairs: | Dr. James J. Demarest IBM, Albany, NY Ms. Carol Boye IBM, Albany, NY | |||
| 1:20 PM | 2.1 | Magnetic Microscopy for 3D Structures: Use of the Simulation Approach for the Precise Localization of Deep Buried Weak Currents | ||
| 1:45 PM | 2.2 | Advanced Sample Preparation Method for Lead Free Bump IMC and Solder Grain Image Enhancement | ||
| 2:10 PM | 2.3 | Extending Acoustic Microscopy for Comprehensive Failure Analysis Applications | ||