Time Resolved Imaging Solving FPGA Logic Fault Localization by Pattern Matching Technique

Tuesday, November 13, 2012: 4:15 PM

101AB (Phoenix Convention Center)

Mr. Guillaume Bascoul , Centre National d'Etudes Spatiales (CNES), Toulouse, France

Mr. Jérome DiBattista , Thales Communication and Security, Toulouse, France

Mr. Philippe Perdu , Centre National d'Etudes Spatiales (CNES), Toulouse, France

12.4 Time Resolved Imaging Solving FPGA Logic Fault Localization by Pattern Matching Technique