Dr. SH Goh

Phd
GLOBALFOUNDRIES
Technology Development- New Technology Prototyping
60 Woodlands Industrial Park D Street 2
Singapore Singapore 738406

Papers:
3.2 Evolution of Wafer Level Tester- Based Diagnostic System: More Than Just a Dynamic Electrical Fault Isolation Tool 3.4 Leveraging Root Cause Deconvolution Analysis for Logic Yield Ramping 5.2 Open Failure Diagnosis Candidate Selection Based On Passive Voltage Contrast Potential and Processing Cost 10.9 Advanced CMOS Device Fault Isolation Using Frequency Mapping On Passive Structures Test Fundamentals and Implementation of Wafer Level Tester-Based Failure Analysis