New Insight into Interconnect Defect Analysis for DRAM

Wednesday, November 8, 2017
Mr. Youngil Kim , Samsung Electronics, Hwaseong, Korea, Republic of (South)
Mr. Hyungchae Jeon , Samsung Electronics, Hwaseong, Korea, Republic of (South)
Mr. Jaeguen Chung , Samsung Electronics, Hwaseong, Korea, Republic of (South)

Summary:

This paper present electrical test method that divide weak or strong interconnect defects of DRAM PKG pads. Proposed method is verified with statistical analysis of 800K DRAM chips and physical analysis of failure chips.