Automated Multi-level Circuit Net Trace for Hotspot Analysis
Automated Multi-level Circuit Net Trace for Hotspot Analysis
Monday, November 11, 2019: 10:45 AM
Portland Ballrooms 254-255 (Oregon Convention Center)
Summary:
GDSII layout net trace to postulate the root cause for abnormal hotspots seen on fault isolation is a standard procedure to guide subsequent failure analysis. This work reviews the limitations of current commercial net trace solutions in terms of their capability and efficiency. We present a new automated multi-level methodology that enables net tracing beyond first-level transistors. The concept is achieved using modular standard verification rules, also commonly known as design rule check (DRC) in design verification. This could potentially revolutionize the way layout analysis is to be conducted.
GDSII layout net trace to postulate the root cause for abnormal hotspots seen on fault isolation is a standard procedure to guide subsequent failure analysis. This work reviews the limitations of current commercial net trace solutions in terms of their capability and efficiency. We present a new automated multi-level methodology that enables net tracing beyond first-level transistors. The concept is achieved using modular standard verification rules, also commonly known as design rule check (DRC) in design verification. This could potentially revolutionize the way layout analysis is to be conducted.