CASE STUDIES - FA PROCESS: Cell Charge Loss by Formation of Inversion Channel in DRAM
CASE STUDIES - FA PROCESS: Cell Charge Loss by Formation of Inversion Channel in DRAM
Tuesday, December 8, 2020: 2:35 PM
Summary:
As cell charge in DRAM became lower, an uncommon phenomenon is observed during the charge sharing operation between cell capacitance and bitline capacitance. This phenomenon is seemed as charge loss of cell capacitance that write time is delayed consequentially. The imbalance between stored charge in write operation and served charge in read operation is a major cause of charge loss. This is not exactly like a charge feedthrough, but is the same in effect of inversion channel. Bit flip of data-0 is observed in the case of extreme low cell capacitance that failure level is ppb (parts per billion). Results show that this phenomenon is influenced by cell capacitance, gate/body voltage of cell transistor, and supplied voltage level of bitline sense amplifier.
As cell charge in DRAM became lower, an uncommon phenomenon is observed during the charge sharing operation between cell capacitance and bitline capacitance. This phenomenon is seemed as charge loss of cell capacitance that write time is delayed consequentially. The imbalance between stored charge in write operation and served charge in read operation is a major cause of charge loss. This is not exactly like a charge feedthrough, but is the same in effect of inversion channel. Bit flip of data-0 is observed in the case of extreme low cell capacitance that failure level is ppb (parts per billion). Results show that this phenomenon is influenced by cell capacitance, gate/body voltage of cell transistor, and supplied voltage level of bitline sense amplifier.