Enabling EFA on single DIE

Wednesday, December 9, 2020: 3:30 PM
Dr. Rudolf Schlangen , NVIDIA Corporation, Santa Clara, CA
Chen Chih (Ronan) Chien , NVIDIA Corporation, Hsinchu, Taiwan
Dr. Christopher Nemirow , NVIDIA Corporation, Santa Clara, CA
Eddy Yang , NVIDIA Corporation, Hsinchu, Taiwan
Jiff Cheng , NVIDIA Corporation, Hsinchu, Taiwan
Mr. Neel Leslie , Thermo Fisher Scientific, Fremont, CA
Prasad Sabbineni , Thermo Fisher Scientific, Fremont, CA
Dr. William Lo , NVIDIA Corporation, Santa Clara, CA
Mr. Howard Marks , NVIDIA Corporation, Santa Clara, CA

Summary:

Working on wafer-level has been the only way to do EFA without the need for die-packaging. nVidia successfully used wafer-level EFA during 20nm and 16nm production ramp for yield and process quality related EFA [1, 2, 3]. But increasing die-size, shrinking technology and some aspects of wafer-production made wafer-level EFA less and less productive for us. At the same time, the introduction of Si-interposer based 2.5D packaging (with HBM stacks surrounding our GPU chip), drastically increased packaging times from ~3 days to >3 weeks. The resulting increase in PFA cycle time makes package-level EFA impractical for fast yield improvement. Additionally, having to wait >3 weeks for EFA & debug work of 1st Si is a significant risk for chip bring-up. To address these challenges, we are presenting ways to enable probing of single die for specific tasks during bring-up, but also for more general EFA work. This paper presents results on low-mag PE by using a blank carrier wafer and a new concept of single die fixturing and matching die support HW to allow SIL level EFA.
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