Yield and Failure Analysis of FinFET Source to Drain Leakage in 14nm Technology
Yield and Failure Analysis of FinFET Source to Drain Leakage in 14nm Technology
Wednesday, December 9, 2020: 11:40 AM
Summary:
A new low level systematic voltage sensitive scan chain fail pattern in the wafer donut region was observed at wafer SORT functional test on specific products manufactured with GLOBALFOUNDRIES’s 14nm technology. Fault localization using both Dynamic Laser Stimulation (DLS) and Emission Microscopy (EMMI) was used to localize the failing transistors within the failing scan chain latch on multiple samples. Nano-probing was then performed and identified source to drain leakage in N-type FinFETs. Physical delayering with SEM inspection and FIB cross-section did not reveal any anomaly on the failing transistors. High resolution TEM elemental analysis highlighted the presence of N-type dopant at the top of the leaky Fin. However, after extensive detailed characterization, it was concluded that the N-type dopant signal was likely due to projections from the source/drain regions included in the TEM lamella. Datamining identified the scan chain fail to be occurring uniquely for a specific family of tools used during source/drain implant diffusion activation. For this family of tools the thermal profile is the highest at the wafer donut region, matching the scan chain failure mode pattern. Semiconductor process and device simulations based on the Finite Element Method (FEM) method were performed to compare the source to drain current at different thermal profile conditions and for different dopant concentrations at the Fin top. It confirmed that additional dopant diffusion toward the junction was occurring. Appropriate tool corrective actions were taken and the low level systematic scan chain fail pattern in the wafer donut region was fully resolved.
A new low level systematic voltage sensitive scan chain fail pattern in the wafer donut region was observed at wafer SORT functional test on specific products manufactured with GLOBALFOUNDRIES’s 14nm technology. Fault localization using both Dynamic Laser Stimulation (DLS) and Emission Microscopy (EMMI) was used to localize the failing transistors within the failing scan chain latch on multiple samples. Nano-probing was then performed and identified source to drain leakage in N-type FinFETs. Physical delayering with SEM inspection and FIB cross-section did not reveal any anomaly on the failing transistors. High resolution TEM elemental analysis highlighted the presence of N-type dopant at the top of the leaky Fin. However, after extensive detailed characterization, it was concluded that the N-type dopant signal was likely due to projections from the source/drain regions included in the TEM lamella. Datamining identified the scan chain fail to be occurring uniquely for a specific family of tools used during source/drain implant diffusion activation. For this family of tools the thermal profile is the highest at the wafer donut region, matching the scan chain failure mode pattern. Semiconductor process and device simulations based on the Finite Element Method (FEM) method were performed to compare the source to drain current at different thermal profile conditions and for different dopant concentrations at the Fin top. It confirmed that additional dopant diffusion toward the junction was occurring. Appropriate tool corrective actions were taken and the low level systematic scan chain fail pattern in the wafer donut region was fully resolved.