Wafer Level Monitoring of Optical Insertion Loss during Silicon Photonics Manufacturing
Wafer Level Monitoring of Optical Insertion Loss during Silicon Photonics Manufacturing
Thursday, October 31, 2024: 9:20 AM
The Pointe (Hilton San Diego Bayfront)
Summary:
Monitoring of optical insertion loss of PICs at wafer-level remains one of the significant challenges to deliver known good dies for silicon photonics, especially with edge-coupled optical IOs. In this article we demonstrated the use of a novel system for wafer–level optical edge-coupling insertion loss measurement to identify a fab process marginality issue. Measuring the optical IO insertion loss at wafer level was shown to be effective in capturing process issues that can happen during manufacturing with a relatively fast turnaround time compared to fiber attach. Thanks to this timely finding, we were able to implement a process fix and control limit tightening to ensure good insertion loss across all regions of the wafer.
Monitoring of optical insertion loss of PICs at wafer-level remains one of the significant challenges to deliver known good dies for silicon photonics, especially with edge-coupled optical IOs. In this article we demonstrated the use of a novel system for wafer–level optical edge-coupling insertion loss measurement to identify a fab process marginality issue. Measuring the optical IO insertion loss at wafer level was shown to be effective in capturing process issues that can happen during manufacturing with a relatively fast turnaround time compared to fiber attach. Thanks to this timely finding, we were able to implement a process fix and control limit tightening to ensure good insertion loss across all regions of the wafer.