Invited Talk: Jayant D'Souza, Seimens, presents, "Design-for-diagnosis for effective FA of backside power designs".
Abstract:
Digital designs utilize scan chains as a critical infrastructure to deliver scan tests and diagnose failing devices. In early yield ramp and silicon bring up chain diagnosis is commonly used to root cause process issues. In this talk, I will cover the basics of chain diagnosis and some recent technology advancements in chain diagnosis that have been leveraged in advanced process nodes. With the advent of backside power, optical fault isolation techniques that have been relied upon in conjunction with chain diagnosis might no longer be an option. This places new requirements on chain diagnosis to isolate the failures prior to failure analysis. In this talk, we will talk about design-for-diagnosis techniques that can be used to achieve highly resolved diagnosis reports for designs including those using backside power.
Biography:
Jayant D’Souza is the technical product manager for silicon learning products in the Siemens EDA Tessent® group. He has about 16 years of experience in the design-for-test (DFT), automatic test pattern generation (ATPG), scan diagnosis and yield learning areas. He is currently focused on the application of DFT and scan on defect diagnosis and yield learning. Jayant holds an MSEE degree from the University of North Carolina at Charlotte (USA).
Ms. Lesly Endrinal, Google LLC