International Roadmap for Failure Analysis (IRFA) Keynote: Dr. Zhiyong Ma, Intel
Monday, October 5, 2026 | 2:10 – 3:10 PM | Bridge Hall
Failure Analysis in the CMOS 2.0 Era: Navigating Disruptive Shifts and Technical Challenges
Abstract: As classical 2D planar scaling reaches its physical and economic limits, the semiconductor industry has officially entered the CMOS 2.0 era. Defined by true 3D circuit-level disaggregation, this new paradigm shifts functional optimization into the vertical dimension through GAAFET/CFET architecture, Backside Power Delivery Networks (BSPDN), and high-density heterogeneous integration. While these innovations solve critical signal routing, IR drop, and power density bottlenecks, they fundamentally shatter traditional Failure Analysis (FA) and Fault Isolation (FI) eco-system, workflows and productivity. This keynote addresses three strategic pillars required to navigate the disruptive shifts and technical challenges to embrace accelerated AI-driven technology development cycles. First, we examine how aggressive scaling acts as a catalyst for pushing capability innovation, especially on defect isolation resolution, necessitated by the need to isolate defects buried within dense, multi-layer die stacks. Second, we analyze the disruption caused by Backside Power Delivery Networks (BSPDN) and 3D heterogeneous integration. By shielding traditional optical windows and burying critical interconnects, these technologies render decades of backside-probing methodology obsolete, driving the urgent development of probeless techniques and alternative defect isolation and detection ecosystems. Finally, we discuss the necessity of leveraging Artificial Intelligence (AI) to manage the massive data complexity and thermo-mechanical coupling inherent in heterogeneous systems. The report concludes that the future of reliability lies in a transition from die-level inspection to an AI-augmented, system-level diagnostic paradigm.
Biography: Dr. Zhiyong Ma is a distinguished industry leader with over 30 years of experience in semiconductor metrology, diagnostic capability, and technology development Q&R. Most recently, he served as Corporate Vice President and Director of Technology Development Quality & Reliability and the Foundry Q&R Lab Network at Intel. Throughout his career, Dr. Ma has championed strategic initiatives to advance lab metrology and debug ecosystems, directly supporting the progression of Moore’s Law through yield and reliability optimization. An accomplished scholar, he has co-authored over 40 technical papers and 2 book chapters on silicide technology and thin film kinetics, and served as lead editor of the book Metrology and Diagnostic Techniques for Nanoelectronics. Dr. Ma holds a PhD in Materials Science and Engineering from the University of Illinois at
Urbana-Champaign.