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| Session 6: Die Level Fault Isolation | ||||
| Location: Jr. Ballroom (Worcester's Centrum Centre) | ||||
| (Please check final room assignments on-site). | ||||
| Session Description: This session covers tools, techniques and analysis related to die level fault isolation. This session underlines the interest of ATPG diagnosis, the challenge of stacked device analysis, submicron probing measurements and substrate dislocations. Through related case studies, this session pays attention to fault isolation efficiency, upstream issues (test, sample preparation, sample stimulation), downstream issues (physical analysis) and pay back (usefulness of the fault isolation). | ||||
| Editors: | Dr. Philippe Perdu CNES - French Space Agency, Toulouse, France James Cargo Agere Systems, Allentown, PA Mr. Stanley Swieck Analog Devices, Wilmington, MA Mr. Michael Eskenazi Qualcomm Corporation, San Diego, CA Felix Beaudoin IBM Mr. Ted Hasegawa National Semiconductor, Santa Clara, CA Mr. David Vallett IBM Systems and Technology Group, Essex Jct., VT | |||
| Session Chair: | Dr. Philippe Perdu CNES - French Space Agency, Toulouse, France | |||
| 1:30 PM | 6.1 | PLENARY TALK: Fault Isolation of Large Nets Using Bridging Fault Analysis | ||
| 1:55 PM | 6.2 | PLENARY TALK: Cavity Up and Stack Die Backside FA for Thin Die and High Pin Count Devices | ||
| 2:20 PM | 6.3 | Investigation of Substrate Dislocation Induces Bit Line Soft Fail | ||
| 2:45 PM | 6.4 | Overcoming Environmentally Induced Probe Drift for Sub-300nm Fault Isolation | ||
| 3:10 PM | 6.5 | Dislocation induced leakage of p+-implanted ESD test macros in 90nm technology | ||
| 3:35 PM | Break | |||