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| Session 19: Yield Enhancement | ||||
| Location: North Ballroom (Worcester's Centrum Centre) | ||||
| (Please check final room assignments on-site). | ||||
| Session Description: Topics include improved wafer test methods to enhance the isolation of interconnect defects and reliability issues, enhanced in-line detection methods such as voltage contrast to detect silicon defects, an analysis of a method for in-line repair of defects, and the proposal of a comprehensive failure analysis strategy to address yield ramp in 90 and 65 nm CMOS technologies. All have the common goal of improving yields faster than can be achieved with current techniques. Several case studies are presented to validate the methods used. | ||||
| Editors: | Mr. Ted Hasegawa National Semiconductor, Santa Clara, CA Felix Beaudoin IBM Mr. Michael Eskenazi Qualcomm Corporation, San Diego, CA Mr. Stanley Swieck Analog Devices, Wilmington, MA James Cargo Agere Systems, Allentown, PA Mr. David Vallett IBM Systems and Technology Group, Essex Jct., VT Ms Carol Boye IBM | |||
| Session Chair: | Ms Carol Boye IBM | |||
| 8:00 AM | 19.1 | PLENARY TALK: An effective Failure Analysis Strategy for the successful introduction of new products designed in 90 and 65 nm CMOS technologies | ||
| 8:25 AM | 19.2 | A Novel Approach of Identifying Silicon Defects Using Passive Voltage Contrast Techniques, Leading to Utilization of In-Line SEM Based Voltage Contrast Inspections to Drive Closed Loop Process Optimization and Defect Ellimination | ||
| 8:50 AM | 19.3 | Defect Snap Shot: Quick Isolation and Mapping of Interconnect Defects for Backend Yield Improvement | ||
| 9:15 AM | 19.4 | In-line Repair of Detectable, Same-Level, Killer Defects Affecting IC Chips | ||
| 9:40 AM | 19.5 | Application of innovative wafer-sort test methods for effective fault isolation | ||
| 10:05 AM | Break | |||