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| Session 27: Sample Preparation 2 | ||||
| Location: Jr. Ballroom (Worcester's Centrum Centre) | ||||
| (Please check final room assignments on-site). | ||||
| Session Description: The sample preparation session covers those processes and techniques, excluding system, test or package level analysis, that are enablers and necessary prior for either fault isolation or physical analysis. This year's Sample Preparation sessions include papers on backside sample preparation for electrical characterization, laser ablation silicon thinning for backside analysis, die-level preparation for TEM analysis including in-situ FIB cross-sectional preparation for TEM examination as well as papers on FESEM and STEM analysis. | ||||
| Editors: | Mr. Seth Prejean Advanced Micro Devices, Austin, TX James Cargo Agere Systems, Allentown, PA Mr. Stanley Swieck Analog Devices, Wilmington, MA Mr. Michael Eskenazi Qualcomm Corporation, San Diego, CA Felix Beaudoin IBM Mr. Ted Hasegawa National Semiconductor, Santa Clara, CA Mr. David Vallett IBM Systems and Technology Group, Essex Jct., VT | |||
| Session Chair: | Mr. Edward Keyes Semiconductor Insights, Ottawa, ON, Canada | |||
| 3:05 PM | 27.1 | Silicon Thinning using Ultra-Short Pulse Laser Ablation | ||
| 3:30 PM | 27.2 | Electrical Characterization of the Access Transistor of Deep Trench based DRAM Products via Backside Contacting | ||
| 3:55 PM | 27.3 | Observations of Crystal Damage on Sidewalls of TEM Samples Prepared by FIB Milling | ||
| 4:20 PM | Concluding Remarks | |||