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| Session 3: Die Level Fault Isolation | ||||
| Location: Meeting Room J1-J2 (San Jose McEnery Convention Center) | ||||
| (Please check final room assignments on-site). | ||||
| Session Description: The Die Level Fault Isolation session covers those tools, techniques and analysis related to die level fault isolation, including novel investigations related to VLSI (debug, yield enhancements, field returns). It focuses on fault isolation improvements to tools, techniques and FA processes. Technique evaluation and comparison, upstream issues (test, sample preparation, sample stimulation), downstream issues (physical analysis) and pay back (usefulness of the fault isolation) are discussed. | ||||
| Editors: | Jerome Touzel Infineon Technologies AG, Munich, Germany Ms Jing Tian, Ph.D. Credence Systems Corp., Sunnyvale, CA Martine Simard-normandin MuAnalysis Inc., Ottawa, ON, Canada Robert E. Lamothe R&L Technologies, Annapolis, MD Gil Gartiez Tower Semiconductor, Migdal Haemek, Israel Romain Desplats CNES - French Space Agency, Toulouse, France Felix Beaudoin IBM Loren F. Vermont Department of Defense, Fort George G. Meade, MD | |||
| Session Chair: | Felix Beaudoin IBM | |||
| 11:00 AM | SYMP053.4 | Multi-Point Probing on 65nm Silicon Technology using Static IREM-based Methodology | ||
| 11:25 AM | SYMP053.5 | Failure Analysis of Soft Single Column Failure in Advanced 90nm SRAM Device with Internal Probing Techniques | ||
| 11:50 AM | SYMP053.6 | The Effectiveness of OBIRCH Based Fault Isolation for Sub-90 nm CMOS technologies | ||
| 12:15 PM | SYMP053.7 | Dislocation Related Leakage in Advanced CMOS Devices | ||