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| Session 7: Package Level Analysis 1 | ||||
| Location: Trinity Room (Renaissance Austin Hotel) | ||||
| (Please check final room assignments on-site). | ||||
| Session Description: This session will highlight new failure analysis tools, techniques, and applications to device and package fault isolation and analysis. Innovative design to assist in the fault isolation will be discussed. Interconnect reliability and associated failure mechanisms will be presented. The role of materials and the environment in package level failures will also be discussed. Finally, micro-structural analysis of flip chip bumps will be highlighted. | ||||
| Editor: | Dr. Deepak Goyal Intel Corporation, Chandler, AZ | |||
| Session Chairs: | Dr. Deepak Goyal Intel Corporation, Chandler, AZ Ms Zezhong Fu Intel Corporation, Chandler, AZ | |||
| 10:20 AM | Intermittent Failures in High Pin Count Packaging | |||
| 10:45 AM | Microstructure Analysis of Wafer Bump Nodule | |||
| 11:10 AM | Packaging Material has Contributed to High Idd_Pd Failures in CMOS ICs | |||
| 11:35 AM | A New Methodology for Electrical Debugging Short in Packages with Modified Daisy-Chain Die | |||