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| Session 14: Test and Diagnostic, Test and Debug | ||||
| Location: Lalique Ballroom (InterContinental Hotel Dallas) | ||||
| (Please check final room assignments on-site). | ||||
| Session Description: Failure isolation and debug of integrated circuits has become increasingly difficult to perform, and there is a vital need to effectively utilize semiconductor test and to properly interpret test failures. Some test equipment is optimized to process structural and design-for-test based test sequences. Diagnosis software can be used to determine the location and defect mechanisms causing test failures. A variety of test, characterization, and diagnosis techniques now help failure analysis engineers in the process of determining root cause of failing devices, thus accelerating the failure and yield-analysis process. | ||||
| Session Chairs: | Mr. Geir Eide Mentor Graphics, Wilsonville, OR Mr. Mark E. Kimball Maxim Integrated Products, Inc., Hillsboro, OR | |||
| 4:50 PM | 14.1 | Systematic Defect Identification through Layout Snippet Clustering | ||
| 5:15 PM | 14.2 | High Volume Scan FA for Yield Enhancement at the 90nm Node | ||
| 5:40 PM | 14.3 | A Tester-Driven Dynamic Laser Stimulation Technique for Hard Functional Failures | ||
| 6:05 PM | 14.4 | Leveraging the Power Grid for Localizing Trojans and Defects | ||