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21.4 Stress Reduction During Silicon Thinning Using Thermal Relaxation Techniques

Thursday, November 15, 2012: 2:10 PM
101AB (Phoenix Convention Center)
Ms. Heenal Patel , Ultra Tec Manufacturing, Inc., Santa Ana, CA
Mr. Jim Colvin , FA Instruments, San Jose, CA
Mr. Timothy Hazeldine , Ultra Tec Manufacturing, Inc., Santa Ana, CA
See more of: Session 21: Chip Level Sample Prep
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