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21 Session 21: Chip Level Sample Prep

Thursday, November 15, 2012: 12:55 PM-3:10 PM
101AB (Phoenix Convention Center)
Session Chairs:
Mr. Bryan Tracy and Mr. Roger Alvis
12:55 PM
21.1
Alternative Lapping Method to Reduce Edge Rounding Effect
Dr. Hock Guan Ong, Temasek Laboratories @ NTU; Prof. Chee Lip Gan, Temasek Laboratories @ NTU
1:20 PM
21.2
Simple and Fast Backside Sample Preparation Technique for Backside Fault Localization Analysis by Using Chemical Etching Method
Mr. HoonYen Gwee, INFINEON TECHNOLOGIES; KiongKay Ng, INFINEON TECHNOLOGIES
1:45 PM
21.3
Sample Preparation Challenges in WLCSP Epoxy Underfill Coating Removal
Mr. Jason H. Lagar, Analog Devices Inc.; Rudolf A. Sia, Analog Devices Inc.
2:10 PM
21.4
Stress Reduction During Silicon Thinning Using Thermal Relaxation Techniques
Ms. Heenal Patel, Ultra Tec Manufacturing, Inc.; Mr. Jim Colvin, FA Instruments; Mr. Timothy Hazeldine, Ultra Tec Manufacturing, Inc.
2:35 PM
21.5
Non-Chemical Solder Bump Removal Technique for Repackaging Flip Chip ICs
Mr. Mauri Sutton, Medtronic
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