8.7
Backside Sample Preparation Challenges for Fault Localization Analysis of Flip Chip Package
Backside Sample Preparation Challenges for Fault Localization Analysis of Flip Chip Package
Wednesday, November 6, 2013: 3:30 PM
Meeting Room 230A (San Jose McEnery Convention Center)
Summary:
In this paper, two mechanical thinning techniques were applied by using the 3D die curvature thinning and 2D flat thinning on flip chip Si backside. The impact of process parameters on die planarity and fault isolation were also discussed. The experimental results demonstrate the UltraPrep system’s high uniformity cross the large die size and provide a very good solution for fault isolation techniques.
In this paper, two mechanical thinning techniques were applied by using the 3D die curvature thinning and 2D flat thinning on flip chip Si backside. The impact of process parameters on die planarity and fault isolation were also discussed. The experimental results demonstrate the UltraPrep system’s high uniformity cross the large die size and provide a very good solution for fault isolation techniques.