4.1
Geometric Trends in Circuit Edit
Geometric Trends in Circuit Edit
Monday, November 4, 2013: 3:00 PM
Meeting Room 230A (San Jose McEnery Convention Center)
Summary:
In this presentation, we have analyzed the geometries of specific FIB based backside circuit edit activities such as vias, silicon access holes, and depositions across four silicon fabrication technologies covering 180nm, 65nm, 45nm, and 28nm. The details of challenging backside FIB edit geometries will be discussed with specific device modification examples. The goal is to systematically examine a large population of edit requests and determine what scaling challenges will be present in the future.
In this presentation, we have analyzed the geometries of specific FIB based backside circuit edit activities such as vias, silicon access holes, and depositions across four silicon fabrication technologies covering 180nm, 65nm, 45nm, and 28nm. The details of challenging backside FIB edit geometries will be discussed with specific device modification examples. The goal is to systematically examine a large population of edit requests and determine what scaling challenges will be present in the future.