41st International Symposium for Testing and Failure Analysis (November 1 - 5, 2015)

November 01 - 05, 2015

Dr. John Keane

Staff Engineer
Intel Corporation
Logic Technology Development
2501 NW 229th Avenue
Hillsboro, OR
USA 97124

Papers:
1.3 Laser Logic State Imaging Using Transient Voltage Collapse Circuits