Panel Discussion - 1st Silicon Debug: Rapid Identification and Correction of Product Systematic Failures
To meet time-to-market requirements, a company must be successful in identifying the root cause of failure on 1st silicon product at wafer final test. Long diagnostic delays due to lack of preparation, improper skill sets, and inadequate equipment can significantly reduce return on investment. Similarly, deciding on the functional area (fab, design, test) that must implement corrective actions can cause further delays. It is a task with both technical and organizational challenges.
The panel presentations will cover key topics that are essential in achieving successful 1st silicon debug: fault isolation challenges, test coverage, design issues, managing the foundry relationship, and business requirements. This will be followed by a discussion examining how these issues are managed organizationally to insure rapid resolution of 1st silicon failures and successful introduction of new products. Included will be how to settle contention behind contributors to the 1st silicon of a product (both internal and external).
For anyone involved in new product introduction, this will be a panel discussion not to miss!