Sample Prep / 3D Package Prep User Group

Monday, November 7, 2016: 3:40 PM-5:40 PM
108 (Fort Worth Convention Center)
Chairs:  Mr. Nathan Bakken, Physical Debug Technology Development, Intel Corporation, Folsom, CA
Co-chairs:  Dr. Roger Stierman, RJ Stierman Consulting, Dallas, TX
3:40 PM
Using microline indentation to precisely downsize <100-um thin die-out-of-the package; Janet Teshima, LatticeGear
4:00 PM
Pulsed laser preparation of uniform, sub-micrometer remaining silicon over active circuits; Scott Silverman, Varioscale, Inc.
4:20 PM
Submicron prep impact on silicon lateral heat dissipation, junction temperature, and FinFET validation thermal management; Vladimir Vlayuk, Intel Corporation
4:40 PM
Novel sample preparation techniques for Semiconductor Process Technology development and Advanced Packaging Analysis using Plasma FIB; Surendra Madala, Thermo Fisher Scientific
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