Scanning Surface Photo Voltage Microscopy (SSPVM) for Stress Analysis in Nanoscale CMOS Devices

Monday, November 6, 2017: 10:05 AM
Ballroom D (Pasadena Convention Center)
Dr. Daminda Dahanayaka , Globalfoundries, Essex Junction, VT
Mr. Phil Kaszuba , Globalfoundries, Essex Junction, VT
Mr. Leon Moszkowicz , Globalfoundries, Essex Junction, VT
Mr. Randall Wells , Globalfoundries, Essex Junction, VT
Dr. James Slinkman , Globalfoundries, Essex Junction, VT
Prof. Lloyd A. Bumm , University of Oklahoma, Norman, OK


Mechanical stress is one of the major factors in the current design and manufacture of very large scale integrated (VLSI) devices. Mechanical stress in nanoscale silicon technologies can dramatically alter carrier mobility (approximately 25%, dependent on device geometry). This affects the device performance. Current in-line production stress metrology is conducted only at a wafer monitor level. For design purposes, the stress state in active device regions has been inferred from electrical data. The available stress measurement techniques such as micro-Raman spectroscopy, nano-beam diffraction (NBD), and converging electron beam diffraction (CEBD), either do not have adequate resolution or they require complex data interpretation. Therefore, when devices are scaled down, these methods cannot be used for measuring local stress levels present in devices. In this paper we present the proof of concept of instrument development and method for measuring mechanical stress in deep sub-micron silicon devices with high spatial resolution using Scanning Surface Photo Voltage Microscopy (SSPVM).