Characterization of Gate Oxide Pinhole Defect in NMOS FinFET Devices
Characterization of Gate Oxide Pinhole Defect in NMOS FinFET Devices
Monday, November 6, 2017: 3:00 PM
Ballroom C (Pasadena Convention Center)
Summary:
This paper demonstrated two cases, one in a logic fail and the other in a memory fail, successfully characterizing the gate oxide pinhole defect in NMOS FinFET devices by the application of nanoprobing technique and electron tomography analysis. Electrical measurements on failing devices by nanoprobing provide guidance for physical analysis. Electron tomography, capable of mitigating the projection issue, enables the physical visualization of oxide pinhole. The combination of these two techniques can result in effective identification of the root cause of tiny pinhole defect.
This paper demonstrated two cases, one in a logic fail and the other in a memory fail, successfully characterizing the gate oxide pinhole defect in NMOS FinFET devices by the application of nanoprobing technique and electron tomography analysis. Electrical measurements on failing devices by nanoprobing provide guidance for physical analysis. Electron tomography, capable of mitigating the projection issue, enables the physical visualization of oxide pinhole. The combination of these two techniques can result in effective identification of the root cause of tiny pinhole defect.