Novel IC Device Repackaging for SIL and Backside Analysis Capability

Thursday, November 9, 2017: 10:15 AM
Ballroom C (Pasadena Convention Center)
Mr. Leandro Muela , ON Semiconductor, Phoenix, AZ
Mr. Raj Kabadi , ON Semiconductor, Phoenix, AZ
Mr. Eric Barbian , ON Semiconductor, Phoenix, AZ


A novel approach for silicon immersed lens (SIL) assisted imaging and back-side analysis of chip-on-board devices is presented. The procedure relies on complete die extraction from original package, and repackage into a FA-friendly Plastic Quad-Flat Package (PQFP) chip carrier with inverted mold configuration, which enables access to the back-side of the die through grinding/polishing or other methods. This procedure also relies on complementing use of device-specific DUT boards and generic arrangement of I/O, ground and power domains, which coupled with a bench-test board equipped with the same pin-out configuration and a custom carrier built specifically for these DUT boards, broadens the use of this solution to an entire family of devices and offers a balance of test capability leading to fault localization success and cost control.