Design for failure analysis in a 24 GHz low-noise amplifier for short range radar applications created in silicon CMOS technology

Monday, November 6, 2017: 12:20 PM
Ballroom A (Pasadena Convention Center)
Dr. Philipp Scholz , Technische Universitaet Berlin, Berlin, Germany
Mr. Soenke Vehring , Technische Universitaet Berlin, Berlin, Germany
Dr. Uwe Kerst , Technische Universitaet Berlin, Berlin, Germany
Dr. Dirk Berger , Technische Universitaet Berlin, Berlin, Germany
Prof. Christian Boit , Technische Universitaet Berlin, Berlin, Germany
Prof. Georg Boeck , Technische Universitaet Berlin, Berlin, Germany
Prof. Friedel Gerfers , Technische Universitaet Berlin, Berlin, Germany

Summary:

As the Internet of Things, smart factories and autonomous driving increase the demand for low-price radar sensors, the authors address this need by developing a 24 GHz short range radar in standard bulk silicon CMOS technology for mass market production. CMOS technology enables cost reduction and efficient system integration compared to former GaAs and current SiGe solutions. Design for failure analysis (DFFA) is implemented in the low-noise amplifier (LNA) of the radar to identify and compensate process deviations. It consists of scalable capacitor structures and is executed using focused ion beam circuit edit. By doing so the design specifications of high gain and low noise of the LNA are reliably met at high yield for the desired operating frequency. The presented DFFA method enables a shift in peak gain by 2.5 GHz. It thereby improves gain and noise figure at 24 GHz by 2 dB and -0.2 dB respectively. The resulting optimized LNA achieves a gain of 20 dB and a noise figure of 3.7 dB matching and surpassing other state-of-the-art works in a single prototyping run.