Capacitance Characterization of Gate to LDD Overlap region to understand subtle fail modes in advanced node technologies

Tuesday, November 12, 2019: 1:25 PM
D 137/138 (Oregon Convention Center)
Mr. Satish Kodali , GLOBALFOUNDRIES Inc., Malta, NY
Dr. Edmund Banghart , GLOBALFOUNDRIES, Malta, NY
Dr. Jagar Singh , GLOBALFOUNDRIES Inc., Malta, NY
Mr. Kevin Davidson , Global Foundries, Malta, NY
Dr. Yu Zhang , GLOBALFOUNDRIES Inc., Malta, NY
Mr. Chong Khiam Oh , GlobalFoundries, Malta, NY

See more of: Nanoprobing and Electrical Characterization II
See more of: Technical Program