Root Cause Analysis of High Input Offset Voltage in Mixed-Signal Design Through Nanoprobing and Cadence Simulation

Tuesday, November 12, 2019: 1:50 PM
D 137/138 (Oregon Convention Center)
Dr. Zhenni Wan , Maxim Integrated, San Jose, CA
Dr. Weikai Yin , Maxim Integrated, San Jose, CA
Mr. Yining Zang , Maxim Integrated, San Jose, CA
Mr. Madhukar Karigerasi , Maxim Integrated, San Jose, CA
Mr. Saurabh Kulkarni , Maxim Integrated, San Jose, CA
Mr. Wui Chung Yap , Maxim Integrated, San Jose, CA
Dr. Dian Yu , Maxim Integrated, San Jose, CA
Dr. Nathan Wang , Maxim Integrated, San Jose, CA
Ms. Qindi Wu , Maxim Integrated, San Jose, CA

See more of: Nanoprobing and Electrical Characterization II
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