A New Approach to IDDQ Failure Fault Localization Using Single Shot Logic (SSL) Patterns
A New Approach to IDDQ Failure Fault Localization Using Single Shot Logic (SSL) Patterns
Wednesday, November 13, 2019: 4:30 PM
D 137/138 (Oregon Convention Center)
Summary:
In this paper the authors will discuss an application of Single Shot Logic (SSL) patterns used for further localizing IDDQ failures using ATPG constraints and targeted faults. This new method provides the analyst a possibility of performing circuit analysis using IDDQ measurement results as a pass/fail criterion rather than logic mismatches. Once a defective area is partially isolated through fault localization, SSL patterns are created to control individual internal node logic states in a deterministic way. IDDQ is measured in each SSL iteration where schematic analysis can further isolate the failure to a specific location. Two cases will be discussed to show how this technique was used on actual failing units, with detailed explanation of the steps performed that led to a more precise determination of the fault location in the suspect cell.
In this paper the authors will discuss an application of Single Shot Logic (SSL) patterns used for further localizing IDDQ failures using ATPG constraints and targeted faults. This new method provides the analyst a possibility of performing circuit analysis using IDDQ measurement results as a pass/fail criterion rather than logic mismatches. Once a defective area is partially isolated through fault localization, SSL patterns are created to control individual internal node logic states in a deterministic way. IDDQ is measured in each SSL iteration where schematic analysis can further isolate the failure to a specific location. Two cases will be discussed to show how this technique was used on actual failing units, with detailed explanation of the steps performed that led to a more precise determination of the fault location in the suspect cell.