V-Pulse Technique For Optical Isolation Of Latchup Triggers In Sub 14 nm Standard-Cell Logic And Memory

Thursday, November 14, 2019: 3:45 PM
F 150/151 (Oregon Convention Center)
Dr. William Lo , NVIDIA, Santa Clara, CA
Puneet Gupta , NVIDIA, Santa Clara, CA
Yen-Tzu Lin , NVIDIA, Santa Clara, CA
Rakshith Venkatesh , NVIDIA, Santa Clara, CA
Dr. Rudolf Schlangen , NVIDIA, Santa Clara, CA
Dr. Jane Li , NVIDIA, Santa Clara, CA
Dr. Chuan Zhang , NVIDIA, Santa Clara, CA
Mr. Howard Lee Marks , NVIDIA, Santa Clara, CA
Bruce Cory , NVIDIA, Santa Clara, CA

Summary:

A technique is introduced for isolating latchup trigger sites in both logic and memory caused by supply overvoltage. Only readily available bench test equipment and standard failure analysis tools are required. A variable-width pulse from a current amplifier is used to rapidly charge the Device Under Test (DUT) capacitance to ramp Vdd. The amplifier can also sink current to rapidly discharge the capacitance. Vdd can stably be brought close to the DUT’s latchup threshold by precise adjustment of the current-pulse width. With the latchup margin reduced in this way, it is then possible to use Continuous-Wave (CW) laser stimulation to induce latchup at the trigger sites. A bench oscilloscope, set to trigger on the characteristic drop in Vdd when latchup occurs, is used to generate a latchup flag for the laser stimulation system. Latchup events are automatically quenched since Vdd is ramped down after each current-pulse. Increasing the pulse width to bring Vdd to the latchup threshold allows the latchup emission to be imaged using Photon Emission Microscopy (PEM). The short duty-cycle voltage pulses made possible by this technique directly contributes to its long-term stability and repeatability.