Product Yield, Test & Diagnostics

Thursday, November 14, 2019: 2:30 PM-4:10 PM
F 150/151 (Oregon Convention Center)
Mr. Jayant DSouza, Mentor Graphics and Mr. Amit Jakati, GLOBALFOUNDRIES
2:30 PM
A Manual Diagnosis Approach Using Targeted Fault Injection and Fault Simulation to Increase the ATPG Diagnostic Resolution in Localizing Faults
Mr. Rommel Estores, ON Semiconductor; Mr. Karo Van Der Gucht, ON Semiconductor
2:55 PM
LADA Synchronization for Symmetric and Asymmetric ATE Test Program Cycles
Mr. Arun Karunanithi, Advanced Micro Devices, Inc.; Mr. Jason Christensen, Advanced Micro Devices, Inc.; Mr. Joseph Caroselli, Advanced Micro Devices, Inc.; Mr. Michell Espitia, Advanced Micro Devices, Inc.
3:20 PM
Utilizing Delta IDDQ to Screen Cell Specific Defects for High Quality and Reliability Applications
Mr. Eric Barbian, ON Semiconductor; Mr. Niel Sanico, ON Semiconductor; Mr. Julien Thiefain, ON Semiconductor; Mr. Andy Koestner, ON Semiconductor
3:45 PM
V-Pulse Technique For Optical Isolation Of Latchup Triggers In Sub 14 nm Standard-Cell Logic And Memory
Dr. William Lo, NVIDIA; Puneet Gupta, NVIDIA; Yen-Tzu Lin, NVIDIA; Rakshith Venkatesh, NVIDIA; Dr. Rudolf Schlangen, NVIDIA; Dr. Jane Li, NVIDIA; Dr. Chuan Zhang, NVIDIA; Mr. Howard Lee Marks, NVIDIA; Bruce Cory, NVIDIA
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