Submicron thinning of finFET devices with high power density observed in 10/7nm process nodes using high aspect ratio trenches

Thursday, November 14, 2019: 8:50 AM
F 150/151 (Oregon Convention Center)
Dr. Nathan Bakken, PhD , Intel Corporation, Folsom, CA
Mr. Vladimir V. Vlasyuk , Intel Corporation, Folsom, CA
Mr. Ilya Artishuk , Intel Corporation, Folsom, CA
Mr. Michael Beal , Intel Corporation, Folsom, CA
Dr. Robert D. Chivas , Varioscale, San Marcos, CA
Dr. Michael DiBattista , Varioscale, San Marcos, CA
Mr. Scott Silverman , Varioscale, San Marcos, CA


Recent trends in FA/FI techniques are driving submicron targets for remaining silicon thickness after sample preparation. The techniques to achieve these higher tolerances at acceptable defect density vary; however, all of them change the thermal/mechanical behavior of the device under test. In this paper, high aspect ratio trenches that can achieve submicron RST without eliminating majority of the bulk substrate will be demonstrated so that the thermal performance can be compared to alternative methods.